1. Field of the Invention
The present invention generally relates to methods and systems for intra-die defect detection.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail.
As design rules shrink, however, semiconductor manufacturing processes may be operating closer to the limitations on the performance capability of the processes. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. Therefore, as design rules shrink, the population of potentially yield relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more and more defects may be detected on the wafers, and correcting the processes to eliminate all of the defects may be difficult and expensive.
Recently, inspection systems and methods are increasingly being designed to focus on the relationship between defect and design since it is the impact on the design for a wafer that will determine whether and how much a defect matters. For example, some methods have been developed for focusing the inspection on only certain portions of the design printed on the wafer. Those portions of the design may be commonly referred to as “patterns of interest” (POIs).
Currently, POI monitoring may be carried out as an extension of the die-to-die difference strategy employed by current wafer inspection systems for finding defects on semiconductor wafers. In this strategy, outlier detection may be performed by taking the difference between the POI on the so-called reference die and the test die. So long as the defect being searched for does not have a common mode that cancels in the difference between the reference and the test images of the POI, this is a sensible way of performing outlier detection.
There can be, however, a number of disadvantages to the above-described methods for POI-based defect detection. For example, it is impossible to perform outlier detection when common mode defect mechanisms cancel out in the difference between the reference and test images of the POI. In addition, it is impossible to perform intra-die inspections with the current methodology of analyzing differences between adjacent dies, which by definition must involve a plurality of dies.
Accordingly, it would be advantageous to develop systems and methods for intra-die defect detection that do not have one or more of the disadvantages described above.